Timing constraints file for hdl coder

HI; I am designing a communication model in Matlab HDL coder (system generator) but I got the problem is a missing constraints file for timing. do any one have the solution for this problem?

sample time=1 for all components.

Regards

[Rakesh Chavan]

Hi,

When you say System Generator are you referring to the Xilinx system generator block. If so when you get the error is it caused by the System generator block? It might be a good idea to check with Xilinx as well if the Xilinx system generator block is throwing the error message.

Can you provide an image of the screenshot of the error message, that might help in understanding the issue you are facing.

Hope this helps

regards

Rakesh

[sameer al-obaidi]

Hi ; Sorry, I designed a model in Matlab HDL coder Simulink block and then generate VHDL code. this code I try to implement in FPGA kintex-7 through Vivado program but the problem is I must set the constraints timing file and other problem so it is a normal problem or not.

Regards

Answer 1

[Kiran Kintali]

In MATLAB to HDL GUI project you can include additional project files related to constraints.

Add these two files in the location where your MATLAB code and HDL Coder project files are located.

insert_timing.tcl

add_file {../../../../clock_constraint.xdc} 

clock_constraint.xdc

create_clock -name MWCLK  -period 4.545 [get_ports clk]